1. Field of the Invention
The present invention relates in general to computer-aided design (CAD) tools for producing layouts based on modular integrated circuit (IC) designs, and in particular to a method for determining whether a buffer inserted by a CAD tool into any signal path within an IC layout will alter the ports of any module of the IC.
2. Description of Related Art
FIG. 1 is a data flow diagram illustrating an integrated circuit design process in which an IC designer initially generates a register transfer language (RTL) netlist 1 describing an IC as a set logic blocks linked though signal paths (“nets”). An RTL netlist 1 often describes the logic blocks somewhat abstractly, using mathematical statements to define the boolean logic they are to carry out. However after having created RTL netlist 1, the designer may employ a synthesis tool 2 to convert the RTL level netlist into a “gate level” netlist 4 describing the logic blocks more concretely by referencing the particular circuit devices that are to implement the logic.
As illustrated in FIG. 2, the gate level netlist 4 of FIG. 1 typically organizes the IC design 10 into a hierarchy of interconnected leaf cells 12 and modules 14. The leaf cells 12, represented by small circles in FIG. 1, are standard circuit components described by entries in a cell library 3 (FIG. 1). Thus rather than directly describing each leaf cell 12, gate level netlist 4 indirectly describes the cell by referencing its corresponding entry in cell library 3. Leaf cells 12 may range from small standard circuit components such as individual transistors and logic gates, up to very large components such random access memories and microprocessors. Gate level netlist 3 organizes the cells 12 forming the IC into a hierarchy of modules 14 with each module 14 residing at any given level of the design hierarchy being formed by a set of interconnected leaf cells and/or modules residing at a next lower level of the hierarchy.
Although gate level netlist 4 identifies the cells forming the IC and names the nets that carry signals between their terminals, it does not describe how the components are to be arranged in a semiconductor substrate and does not indicate how the nets that interconnect them are to be implemented within the substrate. Therefore, after creating gate level netlist 4, the designer uses a layout tool 5 (FIG. 1) to generate a layout 6 for the IC design described by gate level netlist 4. Layout 6 describes how and where each cell is to be formed in a semiconductor substrate and indicates how the nets interconnecting them are to be formed and routed. Layout tool 5 consults cell library 3 to determine the size, shape and internal layout of each leaf cell. As it designs the nets interconnecting cell terminals, layout tool 5 tries to satisfy various constraints 7 the designer places on cell placement and path routing. Layout “tool” 5 may be implemented as a collection of separate tools for carrying out all the various procedures needed to convert a gate level netlist 4 into IC layout 6 in a manner that satisfies constraints 7 including, for example, tools for floor planning, placement and routing, clock tree synthesis, and timing analysis.
During the design process, the designer employs simulation and verification tools 11 to check the IC design specified by RTL and gate level netlists 1 and 4 to determine whether they describe an IC, or selected modules thereof will behave as expected. After layout tool 5 generates IC layout 6, a netlist compiler 8 processes layout 6 to produce another “layout level” netlist 9 modeling the circuit as a set of library cells interconnected by the nets designed by layout tool 5. The inclusion of behavioral models of the nets renders layout level netlist 9 a more accurate model of the behavior of the IC than RTL and gate level netlists 1 and 4. The designer may again employ simulation and verification tools 11 to determine whether the IC the layout level netlist 9 describes will behave as expected.
RTL level and gate level netlists 1 and 4 IC usually describe an IC as a modular hierarchy because the designer usually finds a hierarchical IC design easier to comprehend and manipulate than a “flat” design consisting only of interconnected leaf cells that are not organized into modules. A designer often creates, simulates and verifies each module separately before assembling them into the full netlist description of the IC.
However a typical layout tool 5 ignores the modular, hierarchical nature of the IC design described by gate level netlist 4 and places each leaf cell without regard to its position in the modular design hierarchy. Thus leaf cells forming separate modules can be intermingled to some extent within layout 6. The layout level netlist 8 derived from flat layout 6 therefore typically describes a flat IC design, rather than a hierarchical IC design. The loss of modularity of the layout level netlist version of the IC design makes it difficult for the designer to separately simulate or verify the behavior of each module of the design because the modules no longer exist as identifiable entities at the layout level of the design. Thus the designer is unable to easily compare synthesized behavior of any particular module of the RTL or gate level netlist design with the collective behavior of cells of the layout level netlist design that would otherwise have formed that module.
U.S. patent application Ser. No. 10/117,761, entitled “IC Layout System Employing a Hierarchical Database”, filed Apr. 3, 2002 and incorporated by reference herein, describes a layout tool that compiles gate level netlist 4 into a hierarchical database 13 (as depicted in FIG. 1 herein) that keeps track not only of the position of each cell within layout 6 but also of the position of each cell of the design within the modular hierarchy defined by 4 gate level netlist 4. With such information available in database 13, the designer may direct layout tool 5 to place cells forming selected modules within separate and distinct areas of the semiconductor substrate. Although such restrictions on cell placement can make it more difficult for layout tool 5 to place and route the IC design, restricting selected modules to distinct areas of the substrate provides some advantages. For example, when the design of a module placed in a distinct area of a substrate is changed, layout tool 5 may be able to subsequently modify the layout of that module only without having to modify the layout of any other portion of the IC, provided that the dimensions of the space needed to contain the revised module and the number, nature and position of the module's input and output (I/O) terminals (ports) remain unchanged.
A hierarchical database 13 that remembers how cells are organized in the modular design hierarchy also enables netlist compiler 8 to produce a layout level netlist 9 in which cells are organized into a modular hierarchy that is analogous to that of and gate level netlist 4. This would make it easier for the designer to compare simulation and verification results of the gate and layout level netlists 4 and 9 for all modules, even modules that are not placed in distinct areas of the substrate. Unfortunately, in the course of generating layout 6, layout tool 5 can alter the definition of a module in a way that makes it more difficult to compare simulator results for that module before and after placement.
As discussed above, gate level netlist 4 defines each module residing at any given level of the hierarchy as being a collection of interconnected leaf cells and/or other modules residing at a lower level of the hierarchy. A module's “ports” are the input/output terminals of the module that are connected to the nets linking the module's cells with cells of other modules. Those module ports form a part of a module's definition in RTL and gate level netlists 1 and 4. When a simulator 11 simulates the behavior of a particular module described by the RTL or gate level netlist 1 or 4, it generates data describing the behavior of signals passing in an out of the module ports via those nets. To make it easy to compare results of simulating a corresponding module described by layout level netlist 9, that layout level module should include the same set of ports as the corresponding module described by RTL and gate level netlists 1 and 4.
However, in the course of designing the nets that interconnect the cells forming the modules, layout tool 5 can alter the number and nature of ports a module may need to accommodate one or more of the nets by inserting buffers into the nets to decrease signal path delays. Even though compiler 8 may be able to compile layout 6 into a hierarchical layout level netlist 9, simulation and verification results of some of the modules described by layout level netlist 9 may not be directly comparable with simulation and verification results of corresponding modules described by the RTL and layout level netlists 1 and 4 because corresponding modules may not have the same set of ports.
FIG. 3 illustrates a hierarchy of modules A–E as might be depicted by gate level netlist 4 of FIG. 1. Module A includes a pair of gate cells 18 and 19, and modules B and C include gate cells 20 and 21, respectively. Within the design hierarchy defined by gate level netlist 4 of FIG. 1, modules B and C are submodules (“descendants”) of a common “ancestor” module D, and modules A and D are in turn descendants of their common ancestor module E. The output of cell 18 drives inputs of cells 19–21 via a common net 22 entering the modules though various ports P1–P4. While gate level netlist 4 describes modules A–D as having ports P1–P4, respectively, interconnected by net 22, it does not place any restriction on the manner in which layout tool 5 might route signal paths forming net 22 between modules ports and to the gate terminals within the modules.
A designer will often want delays through selected paths between cells within the IC to remain below specified maximum path delays and will therefore impose constraints 7 (FIG. 1) on the layout directing layout tool 5 to keep those signal path delays within the specified maximums. Therefore after layout tool 5 generates layout 6, it employs a timing analysis tool to calculate the delays within the routing paths of interest based on the physical characteristics of the paths. Where path delays are excessive, layout tool 5 inserts buffers in various segments of the signal paths as necessary to reduce path delays. The capacitance of a signal path contributes to signal path delay by increasing the rise and fall time of signal edges, and when layout tool 5 places a buffer in a path segment, the buffer supplies additional charging current that reduces signal rise and fall times, thereby reducing path delay.
When layout tool 5 inserts a buffer in a signal path, it updates hierarchical database 13 to indicate that the buffer has been incorporated into the IC and assigns the buffer to a particular module of the hierarchical design. Compiler 8 thereafter adds the buffer to the indicated module when generating layout level netlist 9. Simulation and verification tools 11 may then account for the affects of the inserted buffer when simulating or verifying module behavior.
Since adding a buffer to a module of layout level netlist 9 does not alter the logic of a module, the buffer does not necessarily alter the module's definition in a way that renders simulation and verification results for that module any less comparable with simulation and verification results for a corresponding module of gate level netlist 4. However depending on how a signal path is routed within and between modules, depending on which segment of the signal path receives the buffer insertion, and depending on the module to which the inserted buffer is assigned, insertion of the buffer can force compiler 8 to alter the number of ports of one or more modules of layout level netlist 9 needed to accommodate the net. When simulating and verifying behavior of a module, the designer is usually interested in the behavior of the signal appearing at the module's ports. Thus when the layout tool 5 alters the number of ports of a module, it becomes more difficult for the designer to compare gate level and layout level simulation and verification results. Changing the number of ports of a module during the layout process also makes it impossible to alter the layout of that module only without having to also alter the layout of other modules that communicate with it through those ports.
FIG. 5 illustrates how layout tool 5 might generate a modular netlist from the layout of FIG. 4 after the layout tool has inserted a buffer 24 in the net to decrease the path delay from cell 18 to cells 20 and 21. In this example layout tool 5 has assigned buffer 24 to a portion of module E that is external to its descendant modules A and D. Here the insertion of buffer 24 into the net in module E outside of modules A or D does not affect the number of ports of any module. As illustrated in FIGS. 6 and 7, layout tool 5 could also have assigned buffer 24 to a portion of module D outside modules B and C or to module A without having affected the nature or number or ports of any module.
FIG. 8 illustrates an alternative in which layout tool 5 assigns buffer 24 to module B. This alternative forces compiler 8 to increase the number of ports of module B from one to two in layout level netlist 9 because it has to “split” port P2 into two separate ports. In such case, simulation and verification results for module B of layout level netlist 9 of FIG. 1 would not be port-by-port comparable with simulation and verification results for the corresponding module B of the RTL and gate level netlist 1 and 4 as depicted in FIG. 3.
FIGS. 4–8 demonstrate that the insertion of buffer 24 into the net linking cell 18 to cells 20 and 21 may or may not require compiler 8 to alter the number of ports for module B, depending in part on the module to which the inserted buffer 24 is assigned. With buffer 24 assigned to module A as in FIG. 7, no change is required in the number of module ports. However with the buffer assigned to module B as in FIG. 8, there is no way for compiler 8 to create a module B in layout level netlist 9 having only a single port associated with the net linking cell 18 to cells 19–21.
FIG. 9 illustrates another net layout tool 5 might create to link cell 18 to cells 19–21. FIGS. 10–13 illustrate alternative approaches layout tool 5 might take for reducing path delay from cell 18 to cells 19 and 21 without affecting the path delay to cell 20. In FIG. 10 a buffer 26 inserted into segment 27 is assigned to module A. This buffer insertion plan requires compiler 8 to unacceptably split port P1 of module A and port P4 of module D, thereby adversely affecting the module definition of both ports. FIG. 11 shows that assigning buffer 26 to module E at the same hierarchical level as modules A and D splits ports P1 and P4. Assigning buffer 26 to module A would also split ports P1 and P4.
FIG. 12 illustrates a buffer insertion plan in which layout tool 5 inserts separate buffers 28 and 30 into segments 29 and 31 of the network of FIG. 9. This approach reduces signal path delays from cell 18 to cell 19 and 21 but does not split any module ports. Although port P1 appears to be split in FIG. 12, compiler 8 would not treat the two occurrences of port P1 as separate ports because segment 27 ties them together so the two P1 ports convey the same signal. The same is true with respect to port P4.
FIGS. 9–11 demonstrate that in some cases inserting a buffer into one segment of a net will change the number of ports of one or more modules regardless of the module to which the buffer is assigned. FIGS. 9–12 also show that it is possible to insert buffer into some, but not all, segments of a net without splitting module ports.
A buffer insertion can also cause a reduction in the number of module ports. For example assume that, as illustrated in FIG. 13, gate level netlist 4 of FIG. 1 defines module A as having two ports P1A and P1B as illustrated in FIG. 13, and that ports P1A and P1B are tied together in module E, outside of module A. When layout tool 5 inserts a buffer 32 as illustrated in FIG. 14 to decrease the path delay between cells 18 and 19, with buffer 32 being assigned to module E, then there is no change to the number of module A ports. However if layout tool assigns buffer 32 to module A as illustrated in FIG. 15, then compiler 8 of FIG. 1 would have show port P1B as being disconnected from the net. Simulation and verification results for module A of the layout level netlist 9 (FIG. 1) would therefore no longer be directly comparable to the results of a corresponding module A of RTL and gate level netlists 1 and 4 on a port-by-port basis.
The foregoing examples demonstrate that for compiler 8 of FIG. 1 to produce a hierarchical layout level netlist 9 in which each module has the same set of ports as a corresponding module of gate level netlist 4, it is necessary for layout tool 5 to avoid inserting buffers in a way that spits module ports or disconnects them from the net. What is needed is a system for enabling a layout tool to determine when a proposed buffer insertion will split or disconnect a module port so that the layout tool will know to choose an alternative buffer insertion approach when adjusting path delays in any net.